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| 74FR900 9-Bit, 3-Port Latchable Datapath Multiplexer May 1992 Revised August 1999 74FR900 9-Bit, 3-Port Latchable Datapath Multiplexer General Description The 74FR900 is a data bus multiplexer routing any of three 9-bit ports to any other one of the three ports. Readback of data latched from any port onto itself is also possible. The 74FR900 maintains separate control of all latch-enable, output enable and select inputs for maximum flexibility. PINV allows inversion of the data from the C8 to A8 or B8 path. This is useful for control of the parity bit in systems diagnostics. Fairchild's 74FR25900 includes 25 resistors in series with port A and B outputs. Resistors minimize undershoot and ringing which may damage or corrupt sensitive device inputs driven by these ports. Features s 9-bit data ports for systems carrying parity bits s Readback capability for system self checks. s Independent control lines for maximum flexibility s Guaranteed multiple output switching and 250 pF load delays s Outputs optimized for dynamic bus drive capability s PINV parity control facilitates system diagnostics s FR25900 resistor option for driving MOS inputs such as DRAM arrays Ordering Code: Order Number 74FR900SSC Package Number MS48A Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Logic Symbol Connection Diagram Pin Description Pin Names LExx OEx PINV S0, S1 A0-A8 B0-B8 C0-C8 Description Latch Enable Inputs Output Enable Inputs Parity Invert Input Select Inputs Port A Inputs or 3-STATE Outputs Port B Inputs or 3-STATE Outputs Port C Inputs or 3-STATE Outputs (c) 1999 Fairchild Semiconductor Corporation DS010990 www.fairchildsemi.com 74FR900 Functional Description The 74FR900 allows 9-bit data to be transferred from any of three 9-bit I/O ports to either of the two remaining I/O ports. The device employs latches in all paths for either transparent or synchronous operation. Readback capability from any port to itself is also possible. Data transfer within the 74FR900 is controlled through use of the select (S0 and S1) and output-enable (OEA, OEB and OEC) inputs as described in Table 1. Additional control is available by use of the latch-enable inputs (LEAC, LECA, LEBC, LECB) allowing either synchronous or transparent transfers (see Table 2). Table 1 indicates several readback conditions. By latching data on a given port and initiating the readback control configuration, previous data may be read for system verification or diagnostics. This mode may be useful in implementing system diagnostics. Data at the port to be readback must be latched prior to enabling the outputs on that port. If this is not done, a closed data loop will result causing possible data integrity problems. Note that the A and B ports allow readback without affecting any other port. Port C, however, requires interruption of either port A or B to complete its readback path. PINV controls inversion of the C8 bit. A low on PINV allows C8 data to pass unaltered. A high causes inversion of the data. See Table 3. This feature allows forcing of parity errors for use in system diagnostics. This is particularly helpful in 486 processor designs as the 486 does not provide odd/even parity selection internally. TABLE 1. Datapath Control Inputs S0 L L L H H H X X X X L L H H S1 X L O L X O H H H X L H L H OEA H H H L H L L H L H L L X X OEB L H H L L L L H H L X X H H OEC L H L H L L H H H H X L X L Function Port A to Port C Port A to Port B Port A to B+C Port B to Port A Port B to Port C Port B to A+C Port C to Port A Port C to Port B Port C to A+B Outputs Disabled (Readback to A) (Note 1) (Readback to A or C) (Note 1) (Readback to B) (Note 1) (Readback to B or C) (Note 1) Note 1: Readback operation in latched mode only. Transparent operation could result in unpredictable results. TABLE 2. Latch-Enable Control LExx L L H L = LOW Voltage TABLE 3. PINV Control PINV L L H H C8 L H L H A8 or B8 L H H L Input L H X Output L H Q0 H = HIGH Voltage Level Q0 = Output state prior to LExx LOW-to-HIGH transition Logic Diagram www.fairchildsemi.com 2 74FR900 Absolute Maximum Ratings(Note 2) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI IBVIT IIL VID IOD IIH + IOZH IIIL + IOZL IOS ICEX IZZ ICCH ICCL ICCZ Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current Input Leakage Test Output Circuit Leakage Test Output Leakage Current Output Leakage Current Output Short Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current 115 170 147 -100 4.75 3.75 25 -150 -225 50 100 150 200 175 2.4 2.0 0.50 5 7 100 -150 Min 2.0 0.8 -1.2 Typ Max Units V V V V V V A A A A V V A A mA A A mA mA mA Min Min Min Min Max Max Max Max 0.0 0.0 Max Max Max Max 0.0 Max Max Max VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN = -18 mA IOH = -3 mA (An, B n, Cn) IOH = -15 mA (An, Bn, Cn) IOL = 24 mA (An, Bn, Cn) VIN = 2.7V (Control Inputs) VIN = 7.0V (Control Inputs) VIN = 5.5V (An, Bn, Cn) VIN = 0.5V (Control Inputs) IID = 1.9 A, All Other Pins Grounded VIOD = 150 mV, All Other Pins Grounded VOUT =2.7V (An, Bn, Cn) VOUT = 0.5V (An, Bn, Cn) VOUT = 0.0V (An, Bn, Cn) VOUT = VCC (An, Bn, Cn) VOUT = 5.25V (An, Bn, Cn) All Outputs HIGH (Note 4) All Outputs LOW (Note 4) Outputs in 3-STATE Note 4: 2 ports active only 3 www.fairchildsemi.com 74FR900 AC Electrical Characteristics TA = +25C Symbol Parameter Min tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Propagation Delay An or Bn to Cn Cn to An or Bn Propagation Delay C8 to A8 or B8 (PINV HIGH) Propagation Delay An to Bn, Bn to An Propagation Delay LEAC to Cn, LEBC to Cn Propagation Delay LECA to An, LECB to Bn Propagation Delay S0 to Cn Propagation Delay S1 to An or Bn Propagation Delay PINV to A8 or B8 Output Enable Time An, Cn Output Disable Time An, Cn Output Enable Time Bn Output Disable Time Bn 2.5 4.5 4.5 4.8 6.4 6.8 7.5 10.0 10.0 2.5 4.5 4.5 7.5 10.0 10.0 ns ns ns 2.0 4.2 7.0 2.0 7.0 ns VCC = +5.0V CL = 50 pF Typ Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min Max Units 3.0 3.0 3.5 2.0 2.0 1.5 2.0 2.0 6.0 6.0 6.5 5.0 4.0 4.0 5.0 5.0 9.5 10.0 11.0 9.0 6.5 6.0 7.0 7.0 3.0 3.0 3.5 2.0 2.0 1.5 2.0 2.0 9.5 10.0 11.0 9.0 6.5 6.0 7.0 7.0 ns ns ns ns ns ns ns ns AC Operating Requirements TA = +25C Symbol Parameter Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) Setup Time, HIGH or LOW An to LEAC, Bn to LEBC Hold Time, HIGH or LOW An to LEAC, Bn to LEBC Setup Time, HIGH or LOW Cn to LECA or LECB Hold Time, HIGH or LOW Cn to LECA or LECB LE Pulse Width LOW 4.0 VCC = +5.0V CL = 50 pF Typ 2.0 -2.0 1.0 -1.0 4.0 Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 4.0 Max ns Units 1.0 1.0 ns 3.0 3.0 ns 1.0 8.0 1.0 8.0 ns ns Extended AC Electrical Characteristics TA = 0C to +70C VCC = +5.0V Symbol Parameter CL = 50 pF Nine Outputs Switching (Note 5) Min tPLH Propagation Delay Max Min Max TA = 0C to +70C VCC = +5.0V CL = 250 pF (Note 6) Units www.fairchildsemi.com 4 74FR900 Extended AC Electrical Characteristics (Continued) TA = 0C to +70C VCC = +5.0V CL = 50 pF Nine Outputs Switching (Note 5) Min Max 9.0 Min 2.5 Max 10.5 ns TA = 0C to +70C VCC = +5.0V CL = 250 pF (Note 6) Units Symbol Parameter tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ An or Bn to Cn Cn to An or Bn Propagation Delay C8 to A8 or B8 (PINV HIGH) Propagation Delay An to Bn, Bn to An Propagation Delay LEAC to Cn, LEBC to Cn Propagation Delay LECA to An, LECB to Bn Propagation Delay S0 to Cn Propagation Delay S1 to An or Bn Propagation Delay PINV to A8 or B8 Output Enable Time An, Cn Output Disable Time An, Cn Output Enable Time Bn Output Disable Time Bn 2.0 3.5 4.5 4.5 12.0 12.0 5.5 5.5 11.0 13.5 13.5 ns ns ns 3.0 3.0 3.5 11.5 11.0 12.0 4.0 3.0 4.5 2.5 13.5 14.0 15.0 12.0 ns ns ns ns ns ns ns ns 2.0 1.5 2.0 2.0 8.0 6.0 8.0 7.0 Note 5: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase, i.e., all LOW-to-HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc. Note 6: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors standard AC load. This specification pertains to single output switching only. 5 www.fairchildsemi.com 74FR900 9-Bit, 3-Port Latchable Datapath Multiplexer Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS48A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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